As is well-known in the art, arithmetic logic units often perform data processing in a floating point format. Floating point units can be used to perform high precision arithmetic calculations on real, integer, and BCD integers. Moreover, floating point units can be used to perform conversion of numbers between floating point and integer formats.
According to IEEE standard 754, floating point numbers are divided into three sections or fields: a sign field, an exponent field, and a significand or mantissa field. Each field has a finite number of bits, e.g., a mantissa field in an extended precision format has 64 bits. During arithmetic operations that produce a result with a number of bits greater than the number of bits in the field, it is necessary to round the result to fit within the field.
Conventionally, in a floating point unit addition and subtraction operations are performed serially with the rounding operation. Typically, the mantissa of the operands are first normalized, a carry propagate add derives an unrounded result, and a rounding unit inspects the unrounded result and other bits, such as the sticky bit and rounding bit, to determine if it is necessary to round up or round down to obtain the final result. The unrounded result from the carry propagate adder is then incremented if the rounding unit indicates that is necessary. Each of the operations performed by the floating point unit to obtain the final result requires a finite amount of time. Because the steps are performed serially, the process is slow. Moreover, the use of a carry propagate adder is costly because it requires a large amount of area on the chip.
Thus, there is need for a floating point unit that performs arithmetic operations, such as addition and subtraction, in a non-serial manner to obtain a final result in an efficient manner. Further, there is a need for a floating point unit that performs arithmetic operations while avoiding the use of a carry propagate adder.